Semiconductor devices with field plates
US8390000B2 · kind B2 · utility
62Cited by
94References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2009 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Jan 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.