Nonvolatile semiconductor device including a field effect transistor having a charge storage layer of predetermined length

US8390053B2 · kind B2 · utility

Assignee

• RENESAS ELECTRONICS CORPORATION · JP

Inventors

• Kenichi Akita · Chiyoda, JP
• Daisuke Okada · Tokyo, JP
• Keisuke Kuwahara · Tokyo, JP
• Yasufumi Morimoto · Ibaraki, JP
• Yasuhiro Shimamoto · Leuven, BE
• Kan Yasui · Kodaira, JP
• Tsuyoshi Arigane · Tokyo, JP
• Tetsuya Ishimaru · Tokyo, JP

Key dates

• Filing date: Aug 8, 2008
• Grant date: Mar 5, 2013
• Expiry date: Apr 1, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/69

Abstract

A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.