Through via recessed reveal structure and method
US8390130B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked assembly includes a stacked structure stacked on a through via recessed reveal structure. The through via recessed reveal structure includes recesses within a backside surface of an electronic component that expose backsides of through vias. Pillars of the stacked structure are attached to the exposed backsides of the through vias through the recesses. The recesses in combination with the pillars work as a lock and key arrangement to insure self-alignment of the pillars with the backsides of the through vias allowing fine pitch interconnections to be realized. Further, by forming the interconnections to the backsides of the through vias within the recesses, the overall thickness of the stacked assembly is minimized. Further still, by forming the interconnections to the backsides of the through vias within the recesses, shorting between adjacent through vias is minimized or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.