Single period phase to digital converter
US8390347B1 · kind B1 · utility
9Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2012 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Feb 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase to digital converter for a digital PLL (Phase Locked Loop) provides an output in the same or single reference clock period for which it is digitizing the phase error information. The phase to digital converter operates on a positive edge of the reference clock and a digital filter operates on the negative edge of the reference clock so the phase correction performed by the PLL occurs in the same reference clock cycle in which the phase to digital converter is digitizing the phase error information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.