Methods for operating a semiconductor device
US8391059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2011 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Nov 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.