Semiconductor memory apparatus
US8391100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2010 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.