Electronic device, integrated circuit and method for selecting of an optimal sampling clock phase
US8391415B2 · kind B2 · utility
1Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2007 |
| Grant date | Mar 5, 2013 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An electronic device comprises a number of sub-systems coupled via an interface. One of the number of sub-systems comprises logic for receiving a frame of input data having a plurality of phases on respective data paths. The electronic device further comprises logic for performing cross correlation on the received input data with a pre-determined bit pattern, operably coupled to selection logic, for selecting a single phase from the plurality of phases sent to the interface to sample the received input data in a middle region of a data bit period in response to the cross correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.