Patent · US Active

Reducing idle leakage power in an IC

US8392728B2 · kind B2 · utility

2Cited by

5References

4Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Lance Hacking · Spanish Fork, US
Belliappa Kuttanna · Austin, US
Rajesh Patel · San Francisco, US
Ashish V. Choubal · Austin, US
Terry Fletcher · Rancho Cordova, US
Steven S. Varnum · Tigard, US
Binta M. Patel · Austin, US

Key dates

Filing date	Dec 22, 2006
Grant date	Mar 5, 2013
Priority date	—
Expiry date	Jun 2, 2029

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.