Device including memory array and method thereof

US8394700B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Gregory James Scott · Inkom, US
• Mark Michael Nelson · Pocatello, US
• Thierry Coffi Herve Yao · Portland, US

Key dates

• Filing date: Apr 22, 2010
• Grant date: Mar 12, 2013
• Expiry date: Oct 21, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/681

Abstract

An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.