Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

US8394712B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Abhishek Dube · Fishkill, US
• Viorel Ontalus · Danbury, US

Key dates

• Filing date: May 5, 2011
• Grant date: Mar 12, 2013
• Expiry date: Sep 5, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.