Processing with reduced line end shortening ratio
US8394724B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2007 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Nov 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.