Inventor · Singapore, SG

Hai Cong

28Patents
6h-index
47Co-inventors
65Inventor score

Filing activity: Jan 29, 2004 → Jul 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7247555B2 Method to control dual damascene trench etch profile and trench depth uniformity Electricity 9 Expired
US8518775B2 Integration of eNVM, RMG, and HKMG modules Electricity 9 Active
US8058123B2 Integrated circuit and method of fabrication thereof Electricity 7 Active
US7892900B2 Integrated circuit system employing sacrificial spacers Electricity 7 Active
US9972775B2 Integrated magnetic random access memory with logic device having low-k interconnects Electricity 6 Active
US7879732B2 Thin film etching method and semiconductor device fabrication using same Electricity 6 Active
US7745320B2 Method for reducing silicide defects in integrated circuits Electricity 5 Active
US10446607B2 Integrated two-terminal device with logic device for embedded application Electricity 4 Active
US8987134B2 Reliable interconnect for semiconductor device Electricity 4 Active
US10461247B2 Integrated magnetic random access memory with logic device having low-K interconnects Electricity 4 Active
US10608046B2 Integrated two-terminal device with logic device for embedded application Electricity 2 Active
US8940637B2 Method for forming through silicon via with wafer backside protection Electricity 2 Active
US8293545B2 Critical dimension for trench and vias Electricity 1 Active
US8546873B2 Integrated circuit and method of fabrication thereof Electricity 1 Active
US9564575B2 Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures Electricity 1 Active
US8737061B2 Heat dissipating apparatus Physics 1 Active
US9520299B2 Etch bias control Electricity 0 Active
US8828858B2 Spacer profile engineering using films with continuously increased etch rate from inner to outer surface Electricity 0 Active
US8836139B2 CD control Electricity 0 Active
US10103097B2 CD control Electricity 0 Active
US8492236B1 Step-like spacer profile Electricity 0 Active
US8394724B2 Processing with reduced line end shortening ratio Electricity 0 Active
US7960283B2 Method for reducing silicide defects in integrated circuits Electricity 0 Active
US9437550B2 TSV without zero alignment marks Electricity 0 Active
US10115625B2 Methods for removal of hard mask Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.