1T1R resistive memory device and fabrication method thereof

US8395139B1 · kind B1 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Hsin-Jung Ho · Taipei, TW
• Chang-Rong Wu · New Taipei, TW
• Wei Chen · Acton, US

Key dates

• Filing date: Dec 6, 2011
• Grant date: Mar 12, 2013
• Expiry date: Dec 6, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.