Semiconductor device and structure

US8395191B2 · kind B2 · utility

Assignee

• Monolithic 3D Inc. · US

Inventors

• Zvi Or-Bach · San Jose, US
• Brian Cronquist · Klamath Falls, US
• Israel Beinglass · Sunnyvale, US
• Jan Lodewijk de Jong · Cupertino, US
• Deepak C. Sekar · Sunnyvale, US
• Zeev Wurman · Palo Alto, US

Key dates

• Filing date: Oct 7, 2010
• Grant date: Mar 12, 2013
• Expiry date: Oct 12, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.