Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip

US8395196B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brian M. Czabaj · South Burlington, US
• James V. Hart, III · San Jose, US
• William J. Murphy · North Ferrisburgh, US
• James S. Nakos · Saint Johnsbury Center, US

Key dates

• Filing date: Nov 16, 2010
• Grant date: Mar 12, 2013
• Expiry date: Apr 15, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/701

Abstract

A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.