Integration process to improve focus leveling within a lot process variation
US8395228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Apr 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/7026
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.