Memory device having a clock skew generator
US8395950B2 · kind B2 · utility
6Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.