Memory system with in stream data encryption/decryption and error correction
US8396208B2 · kind B2 · utility
2Cited by
16References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2005 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Jun 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The throughput of the memory system is improved where error correction of data in a data stream is cryptographically processed with minimal involvement of any controller. To perform error correction when data from the memory cells are read, the bit errors in the data in the data stream passing between the cells and the cryptographic circuit are corrected prior to any cryptographic process performed by the circuit. Preferably the error correction occurs in one or more buffers employed to buffer the data between the cryptographic circuit and the memory where latency is reduced by using multiple buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.