Patent · US Active

Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product

US8397043B2 · kind B2 · utility

1Cited by

9References

19Claims

0Family size

Assignees

Freeescale Semiconductor, Inc. · US
Continental Teves AG & Co. OHG · DE

Inventors

Anthony M. Reipold · Austin, US
Houman Amjadi · Karlsruhe, DE
Lukusa Didier Kabulepa · Langen (Hessen), DE
Andreas Kirschbaum · Darmstadt, DE
Adrian Traskov · Steinbachl, DE

Key dates

Filing date	Dec 17, 2007
Grant date	Mar 12, 2013
Priority date	—
Expiry date	Nov 17, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/1416
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.