Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor

US8397238B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Suresh K. Venkumahanti · Austin, US
• Martin Saint-Laurent · Austin, US
• Lucian Codrescu · Austin, US
• Baker Mohammad · Abu Dhabi, AE

Key dates

• Filing date: Dec 8, 2009
• Grant date: Mar 12, 2013
• Expiry date: Jul 24, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2896
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.