Method for forming pad in wafer with three-dimensional stacking structure
US8399282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01078
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.