Through-silicon via with low-K dielectric liner
US8399354B2 · kind B2 · utility
17Cited by
36References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Feb 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.