Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package

US8399776B2 · kind B2 · utility

Assignee

• ADVANCED SEMICONDUCTOR ENGINEERING, INC. · TW

Inventors

• Bernd Karl Appelt · Pensacola, US
• William T. Chen · Endicott, US
• Calvin Chun Long CHEUNG · San Jose, US
• Shih-Fu Huang · Hefei, CN
• Yuan-Chang Su
• Chia-Cheng Chen · Daxi District, TW
• Ta-Chun Lee · Taipei, TW

Key dates

• Filing date: Sep 18, 2009
• Grant date: Mar 19, 2013
• Expiry date: Dec 22, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.