Output enable signal generation circuit of semiconductor memory
US8400851B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Dec 28, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Jun 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.