Patterned wafer defect inspection system and method
US8401272B2 · kind B2 · utility
1Cited by
7References
21Claims
0Family size
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Key dates
| Filing date | Aug 2, 2007 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/9501
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for inspecting semiconductor devices is provided. The system includes a region system selecting a plurality of regions from a semiconductor wafer. A golden template system generates a region golden template for each region, such as to allow a die image to be compared to golden templates from a plurality of regions. A group golden template system generates a plurality of group golden templates from the region golden templates, such as to allow the die image to be compared to golden templates from a plurality of group golden templates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.