Explicitly regioned memory organization in a network element
US8402248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Oct 16, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.