Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method
US8402407B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.