Register retiming technique
US8402408B1 · kind B1 · utility
15Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.