Method of manufacturing an electronic parts packaging structure
US8402644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Nov 22, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an electronic parts packaging structure including the steps of preparing a plurality of sheet-like units each of which is constructed by a first insulating layer, a wiring formed on one surface of the first insulating layer, electronic parts connected to the wiring, a second insulating layer formed on an one surface side of the first insulating layer to cover the electronic parts, and a connecting portion for connecting electrically the wiring, and stacking mutually the units to arrange directions of unit adjacent in a thickness direction alternately oppositely, and bonding the units such that electronic parts of respective units are electrically connected mutually via connecting portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.