Metal gate transistor and method for fabricating the same
US8404535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Nov 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.