Source/drain extension control for advanced transistors

US8404551B2 · kind B2 · utility

Assignee

• SuVolta, Inc. · US

Inventors

• Pushkar Ranade · Los Gatos, US
• Lucian Shifren · San Jose, US
• Sachin R. Sonkusale · Los Gatos, US

Key dates

• Filing date: Dec 3, 2010
• Grant date: Mar 26, 2013
• Expiry date: Feb 23, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.