Inventor · Los Gatos, CA, US

Pushkar Ranade

69Patents

11h-index

48Co-inventors

74Inventor score

Filing activity: Nov 8, 2002 → Apr 26, 2018

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7598142B2	CMOS device with dual-epi channels and self-aligned contacts	Electricity	133	Active
US6794234B2	Dual work function CMOS gate technology based on metal interdiffusion	Electricity	72	Expired
US6982230B2	Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures	Electricity	65	Expired
US7691752B2	Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby	Electricity	42	Active
US8421162B2	Advanced transistors with punch through suppression	Electricity	26	Active
US8569156B1	Reducing or eliminating pre-amorphization in transistor manufacture	Electricity	19	Active
US9093550B1	Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same	Electricity	18	Active
US8748986B1	Electronic device with controlled threshold voltage	Electricity	15	Active
US8735987B1	CMOS gate stack structures and processes	Electricity	12	Active
US7141858B2	Dual work function CMOS gate technology based on metal interdiffusion	Electricity	11	Expired
US8404551B2	Source/drain extension control for advanced transistors	Electricity	11	Active
US9112057B1	Semiconductor devices with dopant migration suppression and method of fabrication thereof	Electricity	10	Active
US8563384B2	Source/drain extension control for advanced transistors	Electricity	8	Active
US9496261B2	Low power semiconductor transistor structure and method of fabrication thereof	Electricity	7	Active
US9196727B2	High uniformity screen and epitaxial layers for CMOS devices	Electricity	6	Active
US8877619B1	Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom	Electricity	6	Active
US8796048B1	Monitoring and measurement of thin film layers	Electricity	6	Active
US8569128B2	Semiconductor structure and method of fabrication thereof with mixed metal types	Electricity	6	Active
US8614128B1	CMOS structures and processes based on selective thinning	Electricity	6	Active
US8629016B1	Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer	Electricity	5	Active
US8759872B2	Transistor with threshold voltage set notch and method of fabrication thereof	Electricity	5	Active
US9299698B2	Semiconductor structure with multiple transistors having various threshold voltages	Electricity	5	Active
US7861406B2	Method of forming CMOS transistors with dual-metal silicide formed through the contact openings	Emerging Cross-Sectional Technologies	5	Active
US9111785B2	Semiconductor structure with improved channel stack and method for fabrication thereof	Electricity	5	Active
US8937005B2	Reducing or eliminating pre-amorphization in transistor manufacture	Electricity	4	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.