Method of forming poly-si pattern, diode having poly-si pattern, multi-layer cross point resistive memory device having poly-si pattern, and method of manufacturing the diode and the memory device
US8405062B2 · kind B2 · utility
9Cited by
4References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Dec 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a poly-silicon pattern may include forming an amorphous silicon pattern on a lower layer; forming a capping layer on the substrate covering the amorphous silicon pattern; poly-crystallizing the amorphous silicon pattern using an excimer laser annealing process; and removing the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.