Handling layer for transparent substrate
US8405169B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Apr 21, 2031 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/0038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.