Semiconductor package including a stacking element
US8405213B2 · kind B2 · utility
19Cited by
106References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Apr 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.