Obscuring memory access patterns in conjunction with deadlock detection or avoidance
US8407425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Oct 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.