Method and apparatus for calibrating write timing in a memory system
US8407441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.