Low overhead circuit and method for predicting timing errors
US8407540B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318357
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A data processing circuitry includes a data input, a data output and a processing path arranged between the data input and the data output. The circuitry includes a plurality of retention circuits arranged in parallel with the processing path. At least one potential error detecting circuit including a potential error detecting path for transmitting the data signal pending at an input of one of a plurality of synchronization circuits to one of the retention circuits where the potential error detecting path includes delay circuitry for delaying the data. Also included is comparison circuitry for comparing a value of the data signal captured by one of the synchronization circuits with a value of the data signal captured by a corresponding one of the retention circuits. A comparison circuitry is configured to signal a potential error in response to detecting a difference in the captured data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.