Implementing switching factor reduction in LBIST

US8407542B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Steven M. Douskey · Rochester, US
• Ryan A. Fitch · Auburn Hills, US
• Michael J. Hamilton · Rochester, US
• Amanda R. Kaufer · Rochester, US

Key dates

• Filing date: Jul 27, 2010
• Grant date: Mar 26, 2013
• Expiry date: May 19, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/27
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.