On-chip power-up control circuit
US8410833B2 · kind B2 · utility
1Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jun 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.