Memory circuits, systems, and methods for routing the memory circuits
US8411479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.