Semiconductor memory apparatus
US8411512B2 · kind B2 · utility
1Cited by
16References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.