Memory device with boost compensation
US8411518B2 · kind B2 · utility
19Cited by
3References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | May 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.