Hybrid implementation for error correction codes within a non-volatile memory system
US8412879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | May 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for using different error correction code algorithms to encode and to decode contents of blocks within a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing data within a non-volatile memory includes identifying a first block into which the data is to be stored, and obtaining an indicator associated with the first block. A determination may then be made regarding whether the indicator indicates that the data is to be encoded using a first algorithm. The data is encoded using the first algorithm when it is determined that the data is to be encoded using the first algorithm, after which point the data encoded using the first algorithm is written into the first block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.