Method and device for checking the integrity of a logic signal, in particular a clock signal
US8412996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2008 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/07363
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.