Methods of fabricating image sensors including impurity layer isolation regions
US8415189B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/807
Abstract
Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.