Memory device protection layer
US8415734B2 · kind B2 · utility
0Cited by
16References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 7, 2006 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Dec 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
Abstract
A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.