Semiconductor device with a pillar region and method of forming the same
US8415737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2007 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.