Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain

US8415751B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niloy Mukherjee · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Marko Radosavljevic · Portland, US
• Robert S. Chau · Beaverton, US
• Matthew V. Metz · Portland, US

Key dates

• Filing date: Dec 30, 2010
• Grant date: Apr 9, 2013
• Expiry date: Jun 5, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.