Implementing screening for single FET compare of physically unclonable function (PUF)
US8415969B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Oct 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3278
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.